This application claims the priority of Korean Patent Application No. 2001-73736, filed Nov. 26, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a multi-port semiconductor memory device, and more particularly, to a multi-port semiconductor memory device having a reduced bitline voltage offset and method for arranging memory cells thereof.
2. Description of the Related Art
In general, memory cores of semiconductor memory devices are laid out in an array in which each memory cell is connected to a bitline pair and a wordline, and circuits for accessing memory cells are laid out around memory cores. As demands on high speed systems increase, semiconductor memory devices with increasing high speed and low power consumption are needed. Thus, in order to realize high speed and low power consumption in semiconductor devices, a design method, that is, a lay-out method, as well as a semiconductor manufacturing method are also very important.
FIG. 1 shows a circuit diagram of a bit memory cell structure of a multi-port SRAM. FIG. 2 shows a lay-out of a bit memory cell of FIG. 1, and FIG. 3 shows only bitlines in the lay-out of the bit memory cell of FIG. 2.
Referring to FIG. 1, a bit memory cell of a multi-port SRAM includes inverters I1 and I2 constituting a latch, access transistors T1 and T2 that are controlled by a first wordline wl-1 and are connected to a first bitline pair (BIT1, BITB1), and access transistors T3 and T4 that are controlled by a second wordline wl-2 and are connected to a second bitline pair (BIT2, BITB2).
Here, the first bitline pair (BIT1, BITB1) corresponds to a first port, and the second bitline pair (BIT2, BITB2) corresponds to a second port. Also, Ci1 through Ci5 represent interline capacitance occurring between bitlines, and Cg1 through Cg4 represent wire capacitance of bitlines.
Referring to FIGS. 2 and 3, a twisted bitline structure is used such that defects caused by the mismatch of interline capacitance occurring between bitlines of each port in a memory cell of a multi-port SRAM are reduced. On the other hand, a large amount of mismatch of bitline capacitance occurring between ports occurs. Specifically, the capacitance of the first bitline pair (BIT1, BITB1) has a comparatively low value. In contrast, since the second bitline pair (BIT2, BITB2) is twisted and thus has a relatively large length, the capacitance of the second bitline pair (BIT2, BITB2) is larger than the capacitance of the first bitline pair (BIT1, BITB1). Also, a via contact is used in the second bitline pair (BIT2, BITB2) so that the second bitline pair (BIT2, BITB2) can be twisted. In addition, because the length of the second bitline pair (BIT2, BITB2) is great, the resistance of the second bitline pair (BIT2, BITB2) is increased.
Thus, mismatch occurs between the capacitance and the resistance of the first bitline pair (BIT1, BITB1) and between the capacitance and the resistance of the second bitline pair (BIT2, BITB2). As a result, a voltage offset occurs as a bitline voltage builds-up.
FIG. 4 shows a timing diagram illustrating a case where a bitline voltage builds-up at each port in a memory cell of FIG. 1. Referring to FIGS. 1 and 4, the first bitline pair (BIT1, BITB1) and the second bitline pair (BIT2, BITB2) are pre-charged at a power supply voltage VDD level, and the first and second wordlines wl-1 and wl-2 are simultaneously at a logic “high” level at t0. As a result, a bitline voltage builds-up. In this case, if a target different voltage margin of a sense amplifier (not shown) for sensing a voltage of bitlines is set to Δv, the bitline BIT1 at a first port reaches VDD-Δ v at t1, and the bitline BIT2 at a second port reaches VDD-Δ v at t2, which is larger than t1. As such, a voltage offset of Δ v1 occurs. This is why the bitline BIT2 at the second port has a capacitance and resistance larger than the capacitance and resistance of the bitline BIT1 at the first port, as described above.
However, if sense amplifiers for sensing voltages of the first bitline pair (BIT1, BITB1) of the first port and the second bitline pair (BIT2, BITB2) of the second port have the same enabling time, a sense amplifier should be enabled between t0 and t2 at the second port even though the sense amplifier is enabled only between t0 and t1 at the first port. Thus, the sense amplifier is inevitably enabled between t0 and t2 at the first port in the same manner as at the second port. As a result, an access time of the first port increases, and to this end, the operating speed is reduced, and more power corresponding to Δ v1 is consumed at the first port.
FIG. 5 shows a lay-out of a memory cell array of a conventional multi-port SRAM including memory cells of FIG. 2. Referring to FIG. 5, the conventional multi-port SRAM includes a plurality of memory cells 511, 512, 513, and 514, as shown in FIG. 2, and a plurality of flipped memory cells 521, 522, 523, and 524.
The flipped memory cells 521, 522, 523, and 524 are similar to the memory cells 511, 512, 513, and 514 but are rotated in a mode (RX, RY). The memory cells 511, 512, 513, and 514 and the flipped memory cells 521, 522, 523, and 524 are alternately arranged in line in a row direction. Also, the shape in which the memory cells 511, 512, 513, and 514 and the flipped memory cells 521, 522, 523, and 524 are arranged in line in the row direction is iteratively arranged in a column direction.
FIG. 6 shows a lay-out illustrating that one memory cell is connected to one flipped memory cell in FIG. 5, and FIG. 7 shows only bitlines in the lay-out of the memory cells of FIG. 6.
Referring to FIGS. 6 and 7, a first bitline pair (BIT1, BITB1) of a lower memory cell 512 is connected to a first bitline pair (BITB1, BIT1) of an upper flipped memory cell 522, and a second bitline pair (BIT2, BITB2) of the lower memory cell 512 is connected to a second bitline pair (BITB2, BIT2) of the upper flipped memory cell 522.
As a result, lengths of the first bitline pairs (BIT, BITB1) are equalized, and thus the capacitance and resistance of the first bitline pairs (BIT1, BITB1) are equalized. Also, lengths of the second bitline pairs (BIT2, BITB2) are equalized, and thus the capacitance and resistance of the second bitline pairs (BIT2, BITB2) are equalized. That is, the capacitance and resistance between bitline pairs at each port are equalized. However, the lengths of the first bitline pairs (BIT1, BITB1) at the first port and the lengths of the second bitline pairs (BIT2, BITB2) at the second port are different, and thus capacitance and resistance between two ports are different.
As a result, in the memory cell array of the conventional multi-port SRAM shown in FIG. 5, a great difference between the capacitance and resistance of the first port and the capacitance and resistance of the second port occurs. As such, as described above, in the conventional multi-port SRAMs, a voltage offset occurs during a bitline voltage build-up, and as a result, the operating speed is reduced, and power consumption increases.